A time division duplex transmitting/receiving apparatus that includes a receiver, a transmitter, and a switch for switching the receiver and the transmitter by time division duplex is known. FIG. 9 is a configuration diagram of one example of a time division duplex transmitting/receiving apparatus related to the present invention. Referring to FIG. 9, one example of the time division duplex transmitting/receiving apparatus related to the present invention includes a receiver 201, a transmitter 202, and a switch 203.
Further, the receiver 201 includes a low noise amplifier (hereinafter referred to as an LNA) 305, a down converter 306, a variable attenuator 307, a digital down converter (hereinafter referred to as a DDC) module 308, an FPGA 312, and a CPU (Central Processing Unit) 313.
Further, the DDC module 308 includes an A/D (Analog to Digital) converter 309, a DDC unit 310, and an interruption factor register 311. Further, the FPGA 312 includes a buffer 23.
Further, the transmitter 202 includes a power amplifier (hereinafter referred to as a PA) 303, an up-converter 302, and a D/A (Digital to Analog) converter 301.
In this time division duplex transmitting/receiving apparatus, the FPGA 312 receives an interruption signal from the interruption factor register 311 in the DDC module 308, and transmits the interruption signal to the CPU 313. Receiving the interruption signal, the CPU 313 controls the variable attenuator 307 based on the interruption signal to adjust gain.
FIG. 10 is a timing chart showing one example of operations in a time division duplex transmitting/receiving apparatus related to the present invention. FIG. 10 shows a case in which interruption by a received interference wave at the reception time (see FIG. 10(D)), interruption upon completion of measurement of the received power at the reception time (see FIG. 10(B)), and interruption by electric power leaked into a receiving system at the transmission time (see FIG. 10(C)) are detected in the interruption factor register 311. In this case, an interference wave determination window 59 is set so that determination is made for the whole time period.
However, the CPU 313 desires to detect only interruption (see FIG. 10(D)) by the received interference wave at the reception time. This is because the CPU 313 controls the variable attenuator 307 based on the interruption by the received interference wave at the reception time to adjust gain. On the other hand, in this case, interruption (see FIG. 10(B)) upon completion of measurement of received power at the reception time and interruption (see FIG. 10(C)) by electric power leaked into the receiving system at the transmission time are also detected in the CPU 313, which results in false detection.
Further, a radio terminal apparatus for decreasing clock frequencies of a CPU to prevent occurrence of reception noise when received electric field strength is low is known as an example of the related art of the present invention (see e.g., patent literature 1).
The radio terminal apparatus controls clock frequencies in response to the reception slot start interruption, and restores the clock frequencies in response to the reception slot end interruption. The radio terminal apparatus controls the clock frequencies according to the intensity of the reception level.
Further, the invention related to automatic gain control in a communication system using orthogonal frequency division multiplex or time division duplex is disclosed as another example of a related art of the present invention (see e.g., patent literature 2).
This is based on the control of an aspect such as the number of overflows (saturations in the ADC receiver) produced during a predetermined time window and equalization weights. This results in that gain in the receiver is reduced when the number of overflows in the time window is greater than a predetermined threshold value.